Regviz

Freescale Semiconductor /MKV10Z1287 /SIM /SCGC6

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCGC6

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MKV10Z1287/SIM/SCGC6#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FTF 0 (0)DMAMUX 0 (0)FLEXCAN0 0 (0)FTM3 0 (0)FTM4 0 (0)FTM5 0 (0)SPI0 0 (0)PDB1 0 (0)CRC 0 (0)PDB0 0 (0)FTM0 0 (0)FTM1 0 (0)FTM2 0 (0)ADC0 0 (0)ADC1 0 (0)DAC0

FTM1=0, SPI0=0, PDB1=0, ADC1=0, FTM2=0, FLEXCAN0=0, FTF=0, ADC0=0, FTM5=0, FTM3=0, CRC=0, DAC0=0, DMAMUX=0, FTM4=0, PDB0=0, FTM0=0

Description

System Clock Gating Control Register 6

Fields

FTF

Flash Memory Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
DMAMUX

DMA Mux Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
FLEXCAN0

FLEXCAN0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
FTM3

FTM3 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
FTM4

FTM4 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
FTM5

FTM5 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
SPI0

SPI0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PDB1

PDB1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
CRC

CRC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PDB0

PDB0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
FTM0

FTM0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
FTM1

FTM1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
FTM2

FTM2 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
ADC0

ADC0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
ADC1

ADC1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
DAC0

DAC0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data